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<title>MOVD/MOVQ—Move Doubleword/Move Quadword </title></head>
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<h1>MOVD/MOVQ—Move Doubleword/Move Quadword</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/ En</th>
<th>64/32-bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 6E /<em>r</em></p>
<p>MOVD <em>mm, r/m32</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Move doubleword from <em>r/m32</em> to <em>mm</em>.</td></tr>
<tr>
<td>
<p>REX.W + 0F 6E /<em>r</em></p>
<p>MOVQ <em>mm, r/m64</em></p></td>
<td>RM</td>
<td>V/N.E.</td>
<td>MMX</td>
<td>Move quadword from <em>r/m64</em> to <em>mm</em>.</td></tr>
<tr>
<td>
<p>0F 7E /<em>r</em></p>
<p>MOVD <em>r/m32, mm</em></p></td>
<td>MR</td>
<td>V/V</td>
<td>MMX</td>
<td>Move doubleword from <em>mm</em> to <em>r/m32</em>.</td></tr>
<tr>
<td>
<p>REX.W + 0F 7E /<em>r</em></p>
<p>MOVQ <em>r/m64, mm</em></p></td>
<td>MR</td>
<td>V/N.E.</td>
<td>MMX</td>
<td>Move quadword from <em>mm</em> to <em>r/m64</em>.</td></tr>
<tr>
<td>
<p>66 0F 6E /<em>r</em></p>
<p>MOVD <em>xmm</em>, <em>r/m32</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move doubleword from <em>r/m32</em> to <em>xmm</em>.</td></tr>
<tr>
<td>
<p>66 REX.W 0F 6E /<em>r</em></p>
<p>MOVQ <em>xmm</em>, <em>r/m64</em></p></td>
<td>RM</td>
<td>V/N.E.</td>
<td>SSE2</td>
<td>Move quadword from <em>r/m64</em> to <em>xmm</em>.</td></tr>
<tr>
<td>
<p>66 0F 7E /<em>r</em></p>
<p>MOVD <em>r/m32</em>, <em>xmm</em></p></td>
<td>MR</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move doubleword from <em>xmm</em> register to <em>r/m32</em>.</td></tr>
<tr>
<td>
<p> 66 REX.W 0F 7E /<em>r</em></p>
<p>MOVQ <em>r/m64</em>, <em>xmm</em></p></td>
<td>MR</td>
<td>V/N.E.</td>
<td>SSE2</td>
<td>Move quadword from <em>xmm</em> register to <em>r/m64</em>.</td></tr>
<tr>
<td>
<p>VEX.128.66.0F.W0 6E /</p>
<p>VMOVD <em>xmm1, r32/m32</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move doubleword from <em>r/m32</em> to <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.128.66.0F.W1 6E /r</p>
<p>VMOVQ <em>xmm1, r64/m64</em></p></td>
<td>RM</td>
<td>V/N.E<sup>1</sup>.</td>
<td>AVX</td>
<td>Move quadword from <em>r/m64</em> to <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.128.66.0F.W0 7E /r</p>
<p>VMOVD <em>r32/m32, xmm1</em></p></td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move doubleword from <em>xmm1</em> register to <em>r/m32</em>.</td></tr>
<tr>
<td>
<p>VEX.128.66.0F.W1 7E /r</p>
<p>VMOVQ <em>r64/m64, xmm1</em></p>
<p>EVEX.128.66.0F.W0 6E /r VMOVD xmm1, r32/m32</p>
<p>EVEX.128.66.0F.W1 6E /r VMOVQ xmm1, r64/m64</p></td>
<td>
<p>MR</p>
<p>T1S-RM V/V</p>
<p>T1S-RM V/N.E.<sup>1</sup></p></td>
<td>V/N.E<sup>1</sup>.</td>
<td>
<p>AVX</p>
<p>AVX512F</p>
<p>AVX512F</p></td>
<td>
<p>Move quadword from <em>xmm1</em> register to <em>r/m64</em>.</p>
<p>Move doubleword from r/m32 to xmm1.</p>
<p>Move quadword from r/m64 to xmm1.</p></td></tr>
<tr>
<td>EVEX.128.66.0F.W0 7E /r VMOVD r32/m32, xmm1</td>
<td>T1S-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move doubleword from xmm1 register to r/m32.</td></tr>
<tr>
<td>EVEX.128.66.0F.W1 7E /r VMOVQ r64/m64, xmm1</td>
<td>T1S-MR</td>
<td>V/N.E.<sup>1</sup></td>
<td>AVX512F</td>
<td>Move quadword from xmm1 register to r/m64.</td></tr></table>
<p><strong>NOTES: 1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-</strong></p>
<p>sion is used.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>T1S-RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>T1S-MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Copies a doubleword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or 32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword of an MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low doubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot be used to transfer data between MMX technology registers, between XMM registers, between general-purpose registers, or between memory locations.</p>
<p>When the destination operand is an MMX technology register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.</p>
<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
<p>MOVD/Q with XMM destination:</p>
<p>Moves a dword/qword integer from the source operand and stores it in the low 32/64-bits of the destination XMM register. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit memory location.</p>
<p>128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding YMM destination register remain unchanged. Qword operation requires the use of REX.W=1.</p>
<p>VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires the use of VEX.W=1.</p>
<p>EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires the use of EVEX.W=1.</p>
<p>MOVD/Q with 32/64 reg/mem destination:</p>
<p>Stores the low dword/qword of the source XMM register to 32/64-bit memory location or general-purpose register. Qword operation requires the use of REX.W=1, VEX.W=1, or EVEX.W=1.</p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
<p>If VMOVD or VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.</p>
<h2>Operation</h2>
<p><strong>MOVD (when destination operand is MMX technology register)</strong></p>
<pre>    DEST[31:0] ← SRC;
    DEST[63:32] ← 00000000H;</pre>
<p><strong>MOVD (when destination operand is XMM register)</strong></p>
<pre>    DEST[31:0] ← SRC;
    DEST[127:32] ← 000000000000000000000000H;
    DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>MOVD (when source operand is MMX technology or XMM register)</strong></p>
<pre>    DEST ← SRC[31:0];</pre>
<p><strong>VMOVD (VEX-encoded version when destination is an XMM register)</strong></p>
<pre>    DEST[31:0] (cid:197) SRC[31:0]
    DEST[VLMAX-1:32] (cid:197) 0</pre>
<p><strong>MOVQ (when destination operand is XMM register)</strong></p>
<pre>    DEST[63:0] ← SRC[63:0];
    DEST[127:64] ← 0000000000000000H;
    DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>MOVQ (when destination operand is r/m64)</strong></p>
<pre>    DEST[63:0] ← SRC[63:0];</pre>
<p><strong>MOVQ (when source operand is XMM register or r/m64)</strong></p>
<pre>    DEST ← SRC[63:0];</pre>
<p><strong>VMOVQ (VEX-encoded version when destination is an XMM register)</strong></p>
<pre>    DEST[63:0] (cid:197) SRC[63:0]
    DEST[VLMAX-1:64] (cid:197) 0</pre>
<p><strong>VMOVD (EVEX-encoded version when destination is an XMM register)</strong></p>
<pre>DEST[31:0] (cid:197) SRC[31:0]
DEST[511:32] (cid:197) 0H</pre>
<p><strong>VMOVQ (EVEX-encoded version when destination is an XMM register)</strong></p>
<pre>DEST[63:0] (cid:197) SRC[63:0]
DEST[511:64] (cid:197) 0H</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>MOVD:</p>
<p>__m64 _mm_cvtsi32_si64 (int i )</p>
<p>MOVD:</p>
<p>int _mm_cvtsi64_si32 ( __m64m )</p>
<p>MOVD:</p>
<p>__m128i _mm_cvtsi32_si128 (int a)</p>
<p>MOVD:</p>
<p>int _mm_cvtsi128_si32 ( __m128i a)</p>
<p>MOVQ:</p>
<p>__int64 _mm_cvtsi128_si64(__m128i);</p>
<p>MOVQ:</p>
<p>__m128i _mm_cvtsi64_si128(__int64);</p>
<p>VMOVD</p>
<p> __m128i _mm_cvtsi32_si128( int);</p>
<p>VMOVD</p>
<p> int _mm_cvtsi128_si32( __m128i );</p>
<p>VMOVQ</p>
<p> __m128i _mm_cvtsi64_si128 (__int64);</p>
<p>VMOVQ</p>
<p> __int64 _mm_cvtsi128_si64(__m128i );</p>
<p>VMOVQ</p>
<p> __m128i _mm_loadl_epi64( __m128i * s);</p>
<p>VMOVQ</p>
<p> void _mm_storel_epi64( __m128i * d, __m128i s);</p>
<h2>Flags Affected</h2>
<p>None</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 5.</p>
<table class="exception-table">
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E9NF.</td></tr>
<tr>
<td>If VEX.L = 1.</td></tr>
<tr>
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table></body></html>